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Y. Eum, N. Zhang, L. Tang and Franz Franchetti (Proc. High Performance Extreme Computing (HPEC), 2024)
Towards a RISC-V Instruction Set Extension for Multi-word Arithmetic
Comment: Poster with extended abstract
Preprint (427 KB)
Bibtex

Multi-word arithmetic is a method of doing calculations with data which are bigger than what the machine registers can hold. For example, we could do 128-bit arithmetic with a 64-bit machine by using this technique. One application of multi-word arithmetic is in cryptography, since working with large numbers is a critical security feature [1]. Currently, many CPUs and GPUs support multi-word arithmetic by providing a single carry flag. This is useful for implementing simple 128-bit operations such as addition and subtraction, but is limited with more complicated operations such as multiplication or modulo. Contributions. Our key contributions are: • An extension to the RISC-V ISA to accelerate multi-word arithmetic incorporating multiple carry bits to enable modulo and multiplication. • An implementation of the ISA using the Chipyard framework [2] and the RoCC interface, seeing up to 1.5× speedup in clock cycles.

Keywords:
Multi-word arithmetic