Publications

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Corresponding bibtex list 

3D-stacked 

  1. F. Sadi, Lawrence Pileggi and Franz Franchetti
    3D DRAM Based Application Specific Hardware Accelerator for SpMV
    High Performance Extreme Computing Conference (HPEC), 2016
  2. Qiuling Zhu, Berkin Akin, H. E. Sumbul, F. Sadi, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing
    Proc. IEEE International 3D Systems Integration Conference (3DIC), pp. 1-7, 2013
  3. Qiuling Zhu, H. E. Sumbul, F. Sadi, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    Accelerating Sparse Matrix-Matrix Multiplication with 3D-Stacked Logic-in-Memory Hardware
    Proc. High Performance Extreme Computing (HPEC), pp. 1-6, 2013

Acceleration 

  1. F. Sadi
    Accelerating Sparse Matrix Kernels with Co-optimized Architecture
    PhD. thesis, Electrical and Computer Engineering, Carnegie Mellon University, 2018
  2. F. Sadi, Joe Sweeney, S. McMillan, Tze-Meng Low, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV
    Proc. High Performance Extreme Computing (HPEC), 2018
  3. F. Sadi, Lawrence Pileggi and Franz Franchetti
    3D DRAM Based Application Specific Hardware Accelerator for SpMV
    High Performance Extreme Computing Conference (HPEC), 2016
  4. Qi Guo, N. Alachiotis, Berkin Akin, F. Sadi, G. Xu, Tze-Meng Low, Lawrence Pileggi, James C. Hoe and Franz Franchetti
    3D-Stacked Memory-Side Acceleration: Accelerator and System Design
    Proc. Workshop on Near Data Processing (WONDP), 2014
  5. Qiuling Zhu, Berkin Akin, H. E. Sumbul, F. Sadi, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing
    Proc. IEEE International 3D Systems Integration Conference (3DIC), pp. 1-7, 2013
  6. Qiuling Zhu, H. E. Sumbul, F. Sadi, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    Accelerating Sparse Matrix-Matrix Multiplication with 3D-Stacked Logic-in-Memory Hardware
    Proc. High Performance Extreme Computing (HPEC), pp. 1-6, 2013

Algorithm theory and analysis 

  1. F. Sadi, Lawrence Pileggi and Franz Franchetti
    Algorithm and Hardware Co-Optimized Solution for Large SpMV Problems
    Proc. High Performance Extreme Computing (HPEC), IEEE, pp. 1-7, 2017
  2. F. Sadi, Berkin Akin, Thom Popovici, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    Algorithm/Hardware Co-optimized SAR Image Reconstruction with 3D-stacked Logic in Memory
    Proc. IEEE High Performance Extreme Computing (HPEC), 2014

Architecture 

  1. F. Sadi
    Accelerating Sparse Matrix Kernels with Co-optimized Architecture
    PhD. thesis, Electrical and Computer Engineering, Carnegie Mellon University, 2018
  2. Qiuling Zhu, Berkin Akin, H. E. Sumbul, F. Sadi, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing
    Proc. IEEE International 3D Systems Integration Conference (3DIC), pp. 1-7, 2013

DRAM 

  1. Qiuling Zhu, Berkin Akin, H. E. Sumbul, F. Sadi, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing
    Proc. IEEE International 3D Systems Integration Conference (3DIC), pp. 1-7, 2013

Graphs 

  1. F. Sadi, Joe Sweeney, S. McMillan, Tze-Meng Low, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV
    Proc. High Performance Extreme Computing (HPEC), 2018

Hardware 

  1. F. Sadi, Joe Sweeney, S. McMillan, Tze-Meng Low, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV
    Proc. High Performance Extreme Computing (HPEC), 2018
  2. F. Sadi, Lawrence Pileggi and Franz Franchetti
    Algorithm and Hardware Co-Optimized Solution for Large SpMV Problems
    Proc. High Performance Extreme Computing (HPEC), IEEE, pp. 1-7, 2017
  3. Qiuling Zhu, H. E. Sumbul, F. Sadi, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    Accelerating Sparse Matrix-Matrix Multiplication with 3D-Stacked Logic-in-Memory Hardware
    Proc. High Performance Extreme Computing (HPEC), pp. 1-6, 2013

Logic-in-memory 

  1. Qiuling Zhu, Berkin Akin, H. E. Sumbul, F. Sadi, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing
    Proc. IEEE International 3D Systems Integration Conference (3DIC), pp. 1-7, 2013
  2. Qiuling Zhu, H. E. Sumbul, F. Sadi, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    Accelerating Sparse Matrix-Matrix Multiplication with 3D-Stacked Logic-in-Memory Hardware
    Proc. High Performance Extreme Computing (HPEC), pp. 1-6, 2013

Memory 

  1. Qi Guo, N. Alachiotis, Berkin Akin, F. Sadi, G. Xu, Tze-Meng Low, Lawrence Pileggi, James C. Hoe and Franz Franchetti
    3D-Stacked Memory-Side Acceleration: Accelerator and System Design
    Proc. Workshop on Near Data Processing (WONDP), 2014

Merge parallelization 

  1. F. Sadi, Joe Sweeney, Tze-Meng Low, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    Efficient SpMV Operation for Large and Highly Sparse Matrices Using Scalable Multi-way Merge Parallelization
    Proc. MICRO, 2019

Optimizing 

  1. F. Sadi
    Accelerating Sparse Matrix Kernels with Co-optimized Architecture
    PhD. thesis, Electrical and Computer Engineering, Carnegie Mellon University, 2018
  2. F. Sadi, Lawrence Pileggi and Franz Franchetti
    Algorithm and Hardware Co-Optimized Solution for Large SpMV Problems
    Proc. High Performance Extreme Computing (HPEC), IEEE, pp. 1-7, 2017

Scalable 

  1. F. Sadi, Joe Sweeney, Tze-Meng Low, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    Efficient SpMV Operation for Large and Highly Sparse Matrices Using Scalable Multi-way Merge Parallelization
    Proc. MICRO, 2019
  2. F. Sadi, Joe Sweeney, S. McMillan, Tze-Meng Low, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV
    Proc. High Performance Extreme Computing (HPEC), 2018

Sparse matrices 

  1. F. Sadi, Joe Sweeney, Tze-Meng Low, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    Efficient SpMV Operation for Large and Highly Sparse Matrices Using Scalable Multi-way Merge Parallelization
    Proc. MICRO, 2019

SpMV 

  1. F. Sadi, Joe Sweeney, Tze-Meng Low, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    Efficient SpMV Operation for Large and Highly Sparse Matrices Using Scalable Multi-way Merge Parallelization
    Proc. MICRO, 2019
  2. F. Sadi, Joe Sweeney, S. McMillan, Tze-Meng Low, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV
    Proc. High Performance Extreme Computing (HPEC), 2018

SpMV Operation 

  1. F. Sadi, Joe Sweeney, Tze-Meng Low, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    Efficient SpMV Operation for Large and Highly Sparse Matrices Using Scalable Multi-way Merge Parallelization
    Proc. MICRO, 2019
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Electrical and Computer Engineering, Carnegie Mellon University, 2007