Publications

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Corresponding bibtex list 

Acceleration 

  1. L. Tang, S. Chen, K. Harisrikanth, G. Xu, K. Mai and Franz Franchetti
    A High Throughput Hardware Accelerator for FFTW Codelets: A First Look
    Proc. High Performance Extreme Computing (HPEC), 2022
  2. G. Xu, James C. Hoe and Franz Franchetti
    Flexible Hardware Accelerator Design Generation with SPIRAL
    Proc. High Performance Extreme Computing (HPEC), 2022
  3. Qi Guo, N. Alachiotis, Berkin Akin, F. Sadi, G. Xu, Tze-Meng Low, Lawrence Pileggi, James C. Hoe and Franz Franchetti
    3D-Stacked Memory-Side Acceleration: Accelerator and System Design
    Proc. Workshop on Near Data Processing (WONDP), 2014

Architecture 

  1. G. Xu, Franz Franchetti and James C. Hoe
    An Approach to Generating Customized Load-Store Architectures
    PhD. thesis, Electrical and Computer Engineering, Carnegie Mellon University, 2023

Design 

  1. G. Xu, James C. Hoe and Franz Franchetti
    Flexible Hardware Accelerator Design Generation with SPIRAL
    Proc. High Performance Extreme Computing (HPEC), 2022

Fast Fourier Transform 

  1. L. Tang, S. Chen, K. Harisrikanth, G. Xu, K. Mai and Franz Franchetti
    A High Throughput Hardware Accelerator for FFTW Codelets: A First Look
    Proc. High Performance Extreme Computing (HPEC), 2022
  2. G. Xu, Tze-Meng Low, James C. Hoe and Franz Franchetti
    Optimizing FFT Resource Efficiency of FPGA using High-Level Synthesis
    High Performance Extreme Computing Conference (HPEC), 2017

FFT 

  1. L. Tang, S. Chen, K. Harisrikanth, G. Xu, K. Mai and Franz Franchetti
    A High Throughput Hardware Accelerator for FFTW Codelets: A First Look
    Proc. High Performance Extreme Computing (HPEC), 2022

FFTW 

  1. L. Tang, S. Chen, K. Harisrikanth, G. Xu, K. Mai and Franz Franchetti
    A High Throughput Hardware Accelerator for FFTW Codelets: A First Look
    Proc. High Performance Extreme Computing (HPEC), 2022

FPGA 

  1. G. Xu, Tze-Meng Low, James C. Hoe and Franz Franchetti
    Optimizing FFT Resource Efficiency of FPGA using High-Level Synthesis
    High Performance Extreme Computing Conference (HPEC), 2017

Hardware 

  1. L. Tang, S. Chen, K. Harisrikanth, G. Xu, Franz Franchetti and K. Mai
    A 1.19GHz 9.52Gsamples/sec Radix-8 FFT Hardware Accelerator in 28nm
    Proc. Hot Chips Symposium (HCS), 2024

Hardware accelerator 

  1. L. Tang, S. Chen, K. Harisrikanth, G. Xu, Franz Franchetti and K. Mai
    A 1.19GHz 9.52Gsamples/sec Radix-8 FFT Hardware Accelerator in 28nm
    Proc. Hot Chips Symposium (HCS), 2024
  2. G. Xu, James C. Hoe and Franz Franchetti
    Flexible Hardware Accelerator Design Generation with SPIRAL
    Proc. High Performance Extreme Computing (HPEC), 2022

Load-store 

  1. G. Xu, Franz Franchetti and James C. Hoe
    An Approach to Generating Customized Load-Store Architectures
    PhD. thesis, Electrical and Computer Engineering, Carnegie Mellon University, 2023

Memory 

  1. Qi Guo, N. Alachiotis, Berkin Akin, F. Sadi, G. Xu, Tze-Meng Low, Lawrence Pileggi, James C. Hoe and Franz Franchetti
    3D-Stacked Memory-Side Acceleration: Accelerator and System Design
    Proc. Workshop on Near Data Processing (WONDP), 2014

Optimizing 

  1. G. Xu, Tze-Meng Low, James C. Hoe and Franz Franchetti
    Optimizing FFT Resource Efficiency of FPGA using High-Level Synthesis
    High Performance Extreme Computing Conference (HPEC), 2017

SPIRAL 

  1. G. Xu, James C. Hoe and Franz Franchetti
    Flexible Hardware Accelerator Design Generation with SPIRAL
    Proc. High Performance Extreme Computing (HPEC), 2022

Synthesis 

  1. G. Xu, Tze-Meng Low, James C. Hoe and Franz Franchetti
    Optimizing FFT Resource Efficiency of FPGA using High-Level Synthesis
    High Performance Extreme Computing Conference (HPEC), 2017
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Electrical and Computer Engineering, Carnegie Mellon University, 2007