Publications

Filtered as: all types - all years - author: Xu, G. - all keywords
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Corresponding bibtex list 

Acceleration 

1. L. Tang, S. Chen, K. Harisrikanth, G. Xu, K. Mai and Franz Franchetti
   A High Throughput Hardware Accelerator for FFTW Codelets: A First Look
   Proc. High Performance Extreme Computing (HPEC), 2022
   
2. Qi Guo, N. Alachiotis, Berkin Akin, F. Sadi, G. Xu, Tze-Meng Low, Lawrence Pileggi, James C. Hoe and Franz Franchetti
   3D-Stacked Memory-Side Acceleration: Accelerator and System Design
   Proc. Workshop on Near Data Processing (WONDP), 2014
   

Architecture 

1. G. Xu, Franz Franchetti and James C. Hoe
   An Approach to Generating Customized Load-Store Architectures
   PhD. thesis, Electrical and Computer Engineering, Carnegie Mellon University, 2023
   

Fast Fourier Transform 

1. L. Tang, S. Chen, K. Harisrikanth, G. Xu, K. Mai and Franz Franchetti
   A High Throughput Hardware Accelerator for FFTW Codelets: A First Look
   Proc. High Performance Extreme Computing (HPEC), 2022
   
2. G. Xu, Tze-Meng Low, James C. Hoe and Franz Franchetti
   Optimizing FFT Resource Efficiency of FPGA using High-Level Synthesis
   High Performance Extreme Computing Conference (HPEC), 2017
   

FFT 

1. L. Tang, S. Chen, K. Harisrikanth, G. Xu, K. Mai and Franz Franchetti
   A High Throughput Hardware Accelerator for FFTW Codelets: A First Look
   Proc. High Performance Extreme Computing (HPEC), 2022
   

FFTW 

1. L. Tang, S. Chen, K. Harisrikanth, G. Xu, K. Mai and Franz Franchetti
   A High Throughput Hardware Accelerator for FFTW Codelets: A First Look
   Proc. High Performance Extreme Computing (HPEC), 2022
   

FPGA 

1. G. Xu, Tze-Meng Low, James C. Hoe and Franz Franchetti
   Optimizing FFT Resource Efficiency of FPGA using High-Level Synthesis
   High Performance Extreme Computing Conference (HPEC), 2017
   

Load-store 

1. G. Xu, Franz Franchetti and James C. Hoe
   An Approach to Generating Customized Load-Store Architectures
   PhD. thesis, Electrical and Computer Engineering, Carnegie Mellon University, 2023
   

Memory 

1. Qi Guo, N. Alachiotis, Berkin Akin, F. Sadi, G. Xu, Tze-Meng Low, Lawrence Pileggi, James C. Hoe and Franz Franchetti
   3D-Stacked Memory-Side Acceleration: Accelerator and System Design
   Proc. Workshop on Near Data Processing (WONDP), 2014
   

Optimizing 

1. G. Xu, Tze-Meng Low, James C. Hoe and Franz Franchetti
   Optimizing FFT Resource Efficiency of FPGA using High-Level Synthesis
   High Performance Extreme Computing Conference (HPEC), 2017
   

Synthesis 

1. G. Xu, Tze-Meng Low, James C. Hoe and Franz Franchetti
   Optimizing FFT Resource Efficiency of FPGA using High-Level Synthesis
   High Performance Extreme Computing Conference (HPEC), 2017
   

Publication interface designed and implemented by Patra Pantupat, Aliaksei Sandryhaila, and Markus Püschel
Electrical and Computer Engineering, Carnegie Mellon University, 2007