Publications

Filtered as: all types - all years - author: Sadi, F. - all keywords
Corresponding bibtex list 

  1. F. Sadi, Joe Sweeney, Tze-Meng Low, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    Efficient SpMV Operation for Large and Highly Sparse Matrices Using Scalable Multi-way Merge Parallelization
    Proc. MICRO, 2019
  2. F. Sadi
    Accelerating Sparse Matrix Kernels with Co-optimized Architecture
    PhD. thesis, Electrical and Computer Engineering, Carnegie Mellon University, 2018
  3. F. Sadi, Joe Sweeney, S. McMillan, Tze-Meng Low, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    PageRank Acceleration for Large Graphs with Scalable Hardware and Two-Step SpMV
    Proc. High Performance Extreme Computing (HPEC), 2018
  4. F. Sadi, Lawrence Pileggi and Franz Franchetti
    Algorithm and Hardware Co-Optimized Solution for Large SpMV Problems
    Proc. High Performance Extreme Computing (HPEC), IEEE, pp. 1-7, 2017
  5. F. Sadi, Lawrence Pileggi and Franz Franchetti
    3D DRAM Based Application Specific Hardware Accelerator for SpMV
    High Performance Extreme Computing Conference (HPEC), 2016
  6. Qi Guo, N. Alachiotis, Berkin Akin, F. Sadi, G. Xu, Tze-Meng Low, Lawrence Pileggi, James C. Hoe and Franz Franchetti
    3D-Stacked Memory-Side Acceleration: Accelerator and System Design
    Proc. Workshop on Near Data Processing (WONDP), 2014
  7. F. Sadi, Berkin Akin, Thom Popovici, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    Algorithm/Hardware Co-optimized SAR Image Reconstruction with 3D-stacked Logic in Memory
    Proc. IEEE High Performance Extreme Computing (HPEC), 2014
  8. Qiuling Zhu, Berkin Akin, H. E. Sumbul, F. Sadi, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    A 3D-Stacked Logic-in-Memory Accelerator for Application-Specific Data Intensive Computing
    Proc. IEEE International 3D Systems Integration Conference (3DIC), pp. 1-7, 2013
  9. Qiuling Zhu, H. E. Sumbul, F. Sadi, James C. Hoe, Lawrence Pileggi and Franz Franchetti
    Accelerating Sparse Matrix-Matrix Multiplication with 3D-Stacked Logic-in-Memory Hardware
    Proc. High Performance Extreme Computing (HPEC), pp. 1-6, 2013
Publication interface designed and implemented by Patra Pantupat, Aliaksei Sandryhaila, and Markus Püschel
Electrical and Computer Engineering, Carnegie Mellon University, 2007