Our Papers
Yevgen Voronenko and Markus Püschel,
Multiplierless Multiple Constant Multiplication
to appear in ACM Transactions on Algorithms
PDF |
Figures (PNG)
Other Papers
Here we list other papers relevant to the problem of multiple constant multiplication (MCM).
| [1] |
P. R. Cappello and K. Steiglitz.
Some complexity issues in digital signal processing.
IEEE Transactions on Acoustics, Speech, and Signal
Processing, ASSP-32(5):1037-1041, 1984. [ bib ] |
| [2] |
D. R. Bull and D. H. Horrocks.
Primitive operator digital filters.
IEE Proceedings G, 138(3):401-412, 1991. [ bib ] |
| [3] |
A. G. Dempster and M. D. Macleod.
Use of minimum-adder multiplier blocks in FIR digital filters.
IEEE Transactions in Circuits and Systems-II: Analog and
Digital Signal Processing, 42(9):569-577, 1995. [ bib ] |
| [4] |
A. G. Dempster and M. D. Macleod.
Constant integer multiplication using minimum adders.
IEE Proceedings - Circuits, Devices and Systems,
141(5):407-413, 1994. [ bib ] |
| [5] |
O. Gustafsson and L. Wanhammar.
A novel approach to multiple constant multiplication using minimum
spanning trees.
In Proc. Midwest Symposium on Circuits and Systems, 2002. [ bib ] |
| [6] |
O. Gustafsson, A. G. Dempster, and L. Wanhammar.
Extended results for minimum-adder constant integer multipliers.
In Proc. IEEE International Symposium on Circuits and Systems,
2002. [ bib ] |
| [7] |
V. Lefèvre.
Multiplication by an integer constant.
Technical report, INRIA, 2001. [ bib | .html ] |
| [8] |
V. Lefèvre.
Multiplication by an integer constant: Lower bounds on the code
length.
In Proc. 5th Conference on Real Numbers and Computers, 2003. [ bib ] |
| [9] |
R. Pasko, P. Schaumont, V. Derudder, S. Vernalde, and D. Durackova.
A new algorithm for elimination of common subexpressions.
IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems, 18(1):58-68, 1999. [ bib ] |
| [10] |
A. G. Dempster, S. S. Demirsoy, and I. Kale.
Designing multiplier blocks with low logic depth.
In Proc. IEEE International Symposium on Circuits and
Systems, volume 5, pages 773-776, 2002. [ bib ] |
| [11] |
R. I. Hartley.
Subexpression sharing in filters using canonic signed digit
multipliers.
IEEE Transactions on Circuits and Systems II: Analog and
Digital Signal Processing, 43(10):677-688, 1996. [ bib ] |
| [12] |
Hyeong-Ju Kang, Hansoo Kim, and In-Cheol Park.
FIR filter synthesis algorithms for minimizing the delay and the
number of adders.
IEEE Transactions on Circuits and Systems II: Analog and
Digital Signal Processing, 48(8):770-777, 2001. [ bib ] |
| [13] |
D. Knuth.
The Art of Computer Programming: Seminumerical Algorithms,
volume 2.
Addison-Wesley, 1969. [ bib ] |
| [14] |
A. Avizienis.
Signed-digit number representation for fast parallel arithmetic.
IRE Transactions on Electronic Computers, EC-10:389-400, 1961. [ bib ] |
| [15] |
J. O. Coleman.
Cascaded coefficient number systems lead to FIR filters of striking
computational efficiency.
In Proc. International IEEE Conference in Electronics, Circuits,
and Systems, 2001. [ bib ] |
| [16] |
Robert L. Bernstein.
Multiplication by integer constants.
Software - Practice and Experience, 16(7):641-652, 1986. [ bib ] |
| [17] |
A. G. Dempster and M. D. Macleod.
Using all signed-digit representations to design single integer
multipliers using subexpression elimination.
In Proc. IEEE International Symposium on Circuits and
Systems, 2004. [ bib ] |
| [18] |
H. Choo, K. Muhammad, and K. Roy.
Complexity reduction of digital filters using shift inclusive
differential coefficients.
IEEE Transactions on Signal Processing, 52(6):1760-1772,
2004. [ bib ] |
| [19] |
M. R. Garey and D. S. Johnson.
Computers and Intractability: A Guide to the Theory of
NP-Completeness.
W. H. Freeman And Company, New York, 1979. [ bib ] |
| [20] |
Spiral website.
http://www.spiral.net, 2005. [ bib ] |
| [21] |
P. J. Downey, R. Sethi, and R. E. Tarjan.
Variations on the common subexpressions problem.
J. ACM, 27(4):758-771, 1980. [ bib ] |
| [22] |
P. Tummeltshammer, J. C. Hoe, and M. Püschel.
Multiple constant multiplication by time-multiplexed mapping of
addition chains.
In Proc. Design Automation Conference, pages 826-829, 2004. [ bib ] |
| [23] |
H. Wu and M. A. Hasan.
Closed-form expression for the average weight of signed-digit
representations.
IEEE Transactions on Computers, 48:848-851, 1999. [ bib ] |
| [24] |
Y.-J. Chen, S. Oraintara, T. D. Tran, K. Amaratunga, and T. Q. Nguyen.
Multiplierless approximation of transforms with adder constraint.
IEEE Signal Processing Letters, 9(11):344-347, 2002. [ bib ] |
| [25] |
J. Liang and T.D. Tran.
Fast multiplierless approximations of the DCT with the lifting
scheme.
IEEE Transactions on Signal Processing, 49(12):3032-3044,
2001. [ bib ] |
| [26] |
M. Püschel, A. Zelinski, and J. C. Hoe.
Custom-optimized multiplierless implementations of DSP algorithms.
In Proc. Int'l Conf. Computer Aided Design (ICCAD), pages
175-182, 2004. [ bib ] |
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