Publications

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Corresponding bibtex list 

IP cores for FPGA/ASIC 

1. Sung-Chul Han
   A Flexible Decoder and Performance Evaluation of Array-Structured LDPC Codes
   PhD. thesis, Electrical and Computer Engineering, Carnegie Mellon University, 2007
   

LDPC codes 

1. Sung-Chul Han
   A Flexible Decoder and Performance Evaluation of Array-Structured LDPC Codes
   PhD. thesis, Electrical and Computer Engineering, Carnegie Mellon University, 2007
   

Numerical kernels we consider 

1. Sung-Chul Han, Franz Franchetti and Markus Püschel
   Program Generation for the All-Pairs Shortest Path Problem
   Proc. Parallel Architectures and Compilation Techniques (PACT), pp. 222-232, 2006
   

SIMD vectorization 

1. Sung-Chul Han, Franz Franchetti and Markus Püschel
   Program Generation for the All-Pairs Shortest Path Problem
   Proc. Parallel Architectures and Compilation Techniques (PACT), pp. 222-232, 2006
   

Publication interface designed and implemented by Patra Pantupat, Aliaksei Sandryhaila, and Markus Püschel
Electrical and Computer Engineering, Carnegie Mellon University, 2007